The present invention relates to extracting wafer process parameters during integrated circuit (IC) fabrication and, more particularly, to a method and test structure for extracting absolute lateral PNP transistor basewidth information at wafer probe.
In the past, the statistical simulation of bipolar integrated circuit parametric performance often applied some form of Monte Carlo analysis to a manufacturing database of Gummel Poon (GP) model parameters. However, it has been recognized that many of the GP model parameters are strongly correlated and thus cannot be used with Monte Carlo algorithms to provide accurate statistical data.
To resolve these problems with the prior art method of developing statistical data that is useful for the design community in designing and fabricating integrated circuits, a bipolar statistical simulator has been developed which incorporates sets of basically uncorrelated process parameters that can be extracted at the wafer level during manufacturing of integrated circuits. In this approach the GP model parameters are defined as functions of the uncorrelated process parameters. For an example, it has been determined that the saturation current GP model parameter for a lateral PNP transistor formed in an integrated circuit is a function of the uncorrelated actual basewidth of the transistor and the N-type epitaxial doping concentration in which the transistor is formed.
Hence, in order to utilized this new statistical simulation new methods and test structures must be developed into on-line process control die of the IC wafer manufacturing process to extract these uncorrelated process parameters at wafer probe. Thus, a need exists for one such method and test structure for extracting the actual basewidth of a lateral PNP device of an integrated circuit.